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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM32N864/D
Advance Information
256KB Secondary Cache Module
With Tag and Optional Dirty for 486 Processor Systems
These 256K Byte cache modules offer dual asynchronous 32K x 32 banks of memory. There is a 16K x 8 tag memory for main memory cacheability up to 64 Megabytes. The MCM32N865 and MCM32P865 include a 16K x 1 common I/O dirty bit for writeback cache capability. The modules are designed to support common 486 chipsets which utilize chip enable (CEx) byte control and bank write enable (CWEx). The MCM32N864 and MCM32N865 operate at 5 V while the MCM32P864 and MCM32P865 operate at 3.3 V power. PD pins are provided for cache size identification at system startup * 64MB of Cacheable Memory * Low Profile Edge Connector: Burndy Part Number: CELP2X56SC3Z48 * All Inputs and Outputs are TTL Compatible * Three State Outputs * Fast Module Cycle Time: Up to External Processor Bus Speed of 33 MHz * Cache Bank Write, Byte Chip Enable, Bank Output Enable * Decoupling Capacitors are Used for Each Fast Static RAM * High Quality Multi-Layer FR4 PWB With Separate Power and Ground Planes * 5 V and 3.3 V Power Supplies are Supported
MCM32N864 MCM32N865 MCM32P864 MCM32P865
112-LEAD CARD EDGE CASE 1112-01 TOP VIEW 1
45 46
56
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 1 6/95
(c) Motorola, Inc. 1995 MOTOROLA FAST SRAM
MCM32N864*MCM32N865*MCM32P864*MCM32P865 1
PIN ASSIGNMENT CACHE MODULE 112 PIN CARDEDGE TOP VIEW
VSS DQ0 DQ2 DQ4 DQ6 VCC5 NC DQ8 DQ10 DQ12 VSS DQ14 DQ16 DQ18 DQ20 VCC5 DQ22 NC DQ24 DQ26 VSS DQ28 DQ30 CA3B CA3A VCC5 A4 A6 A8 A10 A12 A14 A16 NC VSS NC TDQ0 TDQ2 TDQ4 VSS TDQ6 NC TE TWE VCC5 VSS NC *DIRTYWE NC VCC5 G0 CWE0 PD0 PD2 NC VSS 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 VSS DQ1 DQ3 DQ5 DQ7 VCC3 NC DQ9 DQ11 DQ13 VSS DQ15 DQ17 DQ19 DQ21 VCC3 DQ23 NC DQ25 DQ27 VSS DQ29 DQ31 NC NC VCC3 A5 A7 A9 A11 A13 A15 A17 NC VSS NC TDQ1 TDQ3 TDQ5 VSS TDQ7 DIRTY* NC CE0 VCC3 VSS CE1 CE2 CE3 VCC3 G1 CWE1 PD1 PD3 NC VSS
PD3 NC NC GND
PD2 NC GND GND
PD1 NC NC NC
PD0 NC NC NC
Cache Size -- 256KB 256KB
Dirty -- No Yes
Module No Module 32N864 32P864 32N865 32P865
PIN NAMES
A4 - A17 . . . . . . . . . . . . . . . . . . . . . . Address Inputs CA3A, CA3B . . . . . . . . . . . . . . Bank Address Inputs CWEx . . . . . . . . . . . . . . . . . . . . . Bank Write Enable CEx . . . . . . . . . . . . . . . . . . . . . . . . Byte Chip Enable G0, G1 . . . . . . . . . . . . . . . . . . . Bank Output Enable DQ0 - DQ31 . . . . . . . . . . Cache Data Input/Output TDQ0 - TDQ8 . . . . . . . . . . . Tag Data Input/Output TWE . . . . . . . . . . . . . . . . . . . . . . . . Tag Write Enable TE . . . . . . . . . . . . . . . . . . . . . . . . . . Tag Chip Enable DIRTYWE . . . . . . . . . . . . . . . . . . Dirty Write Enable DIRTY . . . . . . . . . . . . . . . . . . . . . . Dirty Input/Output PD0 - PD3 . . . . . . . . . . . . . . . . . . Presence Detect NC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No Connect VCC5 . . . . . . . . . . . . . . . . . . . . . +5 V Power Supply VCC3 . . . . . . . . . . . . . . . . . . . +3.3 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
* No Connect for MCM32N864 and MCM32P864
MCM32N864*MCM32N865*MCM32P864*MCM32P865 2
MOTOROLA FAST SRAM
MCM32N865 486 256KB CACHE MODULE BLOCK DIAGRAM WITH 8 TAG BITS AND DIRTY
32K x 8 A1 - A14 DQ0 - DQ7 E A0 W G 32K x 8 A1 - A14 DQ0 - DQ7 E A0 W G 32K x 8 A1 - A14 DQ0 - DQ7 E A0 W G 32K x 8 A1 - A14 DQ0 - DQ7 E A0 W CWE0 G0 CA3A DQ0 - DQ7 DQ8 - DQ15 DQ16 - DQ23 DQ24 - DQ31 8 8 8 8 A0 - A13 16K x 1 DIRTY DIRTYWE 74F244 A4 - A17 TDQ0 - TDQ7 TWE 14 A0 - A13 DQ0 - DQ7 W 16K x 8 E TE DQ W E G 32K x 8 A1 - A14 DQ0 - DQ7 E A0 G 32K x 8 A1 - A14 DQ0 - DQ7 E A0 G 32K x 8 A1 - A14 DQ0 - DQ7 E A0 G 32K x 8 A1 - A14 DQ0 - DQ7 E A0 G W CWE1 G1 CA3B W W W
CE0
CE1
CE2
CE3
MOTOROLA FAST SRAM
MCM32N864*MCM32N865*MCM32P864*MCM32P865 3
MCM32N864 486 128KB CACHE MODULE BLOCK DIAGRAM WITH 8 TAG BITS
32K x 8 A1 - A14 DQ0 - DQ7 E A0 W G 32K x 8 A1 - A14 DQ0 - DQ7 E A0 W G 32K x 8 A1 - A14 DQ0 - DQ7 E A0 W G 32K x 8 A1 - A14 DQ0 - DQ7 E A0 W CWE0 G0 CA3A DQ0 - DQ7 DQ8 - DQ15 DQ16 - DQ23 DQ24 - DQ31 8 8 8 8 G 32K x 8 A1 - A14 DQ0 - DQ7 E A0 G 32K x 8 A1 - A14 DQ0 - DQ7 E A0 G 32K x 8 A1 - A14 DQ0 - DQ7 E A0 G 32K x 8 A1 - A14 DQ0 - DQ7 E A0 G W CWE1 G1 CA3B W W W
CE0
CE1
CE2
CE3
74F244 A4 - A17 TDQ0 - TDQ7 TWE 14 A0 - A13 DQ0 - DQ7 W 16K x 8 E TE
MCM32N864*MCM32N865*MCM32P864*MCM32P865 4
MOTOROLA FAST SRAM

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